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Influence of Microstructure on the Electronic Transport Behavior of Microcrystalline Silicon Films

My Thesis: Influence of Microstructure on the Electronic Transport Behavior of Microcrystalline Silicon Films

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My Thesis: Influence of Microstructure on the Electronic Transport Behavior of Microcrystalline Silicon Films from Sanjay Ram

Bimodal CSD in Microcrystalline Silicon

Crystallite Size Distribution in µc-Si:H

Plasma deposition techniques of microcrystalline silicon (µc-Si:H) fabrication inevitably lead to inhomogeneities in the microstructure of the material, as the contents of the constituent phases of mc-Si:H are influenced by the processing history. These inhomogeneities exist at different length scales and require to be studied with the help of different microstructural characterization tools acting at different length scales. An inhomogeneity in the form of a distribution in the sizes of the crystallites (CSD) is one such well-known feature present in plasma deposited µc-Si:H.

Background

Electrical transport in µc-Si:H has been conventionally linked to and studied in the context of changing film crystallinity. In the fully crystalline single-phase µc-Si:H material, there is no appreciable change in crystallinity with film growth. In the absence of an amorphous phase, the CSD and conglomeration of grains in such material may have a significant influence on the electrical transport properties and mechanisms. A detailed knowledge about these microstructural properties would allow a better understanding of the anisotropic nature of electrical transport, which results from the influence of crystalline orientation and the location of grain boundaries on the transport path. With this knowledge, it would be possible to predict the transport behavior in a particular direction, i.e., planar or perpendicular configuration, which is essential for optimization of device performance.

Issues

Conventionally, Raman spectroscopy profiles are deconvoluted assuming a single mean crystallite size and a peak assigned to grain boundary material, and to account for the asymmetric tail, an amorphous phase is included. However, these assumptions could be erroneous for a single phase µc-Si:H material, in which the presence of a CSD is demonstrated by other microstructural characterization studies. The presence of CSD should be accounted for in the analyses of Raman spectra for more physically accurate results and picture of the material structure.

Measured imaginary part of <E₂> spectrum for µc-Si:H sample; and reference spectra of µc-Si, amorphous silicon, and of low-pressure chemical vapor deposited polysilicon with large (pc-Si- l) and fine (pc-Si-f) grains.

What we have done

In our microstructural studies on µc-Si:H, we employed different microstructural characterization tools (spectroscopic ellipsometry, Raman spectroscopy, X-ray diffraction, and atomic force microscopy) to study the presence of CSD.
We acquired quantitative information about the mean crystallite sizes and their volume fractions in highly crystalline µc-Si:H with spectroscopic ellipsometry. Then we determined the actual crystallite size distribution using Raman spectroscopy with the help of a modification in the modeling method.

Corroboration of results from different studies

The results of spectroscopic ellipsometry, X-ray diffraction, and atomic force microscopy demonstrate the presence of a distribution in the sizes of crystallites.

The modeling of spectroscopic ellipsometry results using two types of crystallites having two distinct sizes is corroborated with the deconvolution of experimentally observed RS profiles using a bimodal size distribution of crystallites having two mean sizes, large and small.

The fractional compositional analyses of the films obtained by this methodology are found to be in qualitative agreement with the findings of spectroscopic ellipsometry.

Significance of the results

Our study shows that the appearance of a strong and longer low-frequency tail in Raman profiles measured from film side of single-phase µc-Si:H material, without any distinguishable amorphous hump, can be due to the presence of size distribution in nanocrystallites, instead of a contribution from disordered or amorphous phase.


REFERENCES

Read more about these in these papers:


1. “Evidence of Bimodal Crystallite Size Distribution in µc-Si:H Films”, Sanjay K. Ram, Md. N. Islam, S. Kumar and P. Roca i Cabarrocas, Materials Science and Engineering B (in press, doi: 10.1016/j.mseb.2008.11.048)
5. "Effects of crystallite size distribution on the Raman-scattering profiles of silicon nanostructures", M.N. Islam, A. Pradhan, S. Kumar, J. Appl. Phys. 98 (2005) 024309.

2. “Influence of the statistical shift of Fermi level on the conductivity behavior in microcrystalline silicon”, Sanjay K. Ram, P. Roca i Cabarrocas and S. Kumar, Phys. Rev. B. 77, 045212 (2008).
3. “Structural determination of nanocrystalline Si films using ellipsometry and Raman spectroscopy”, Sanjay K. Ram, Md. N. Islam, S. Kumar, and P. Roca i Cabarrocas, Thin Solid Films 516 (2008) 6863.
4. "Influence of crystallite size distribution on the micro-Raman analysis of porous Si", M.N. Islam, S. Kumar, Appl. Phys. Lett. 78 (2001) 715.

Organic Semiconductors (small molecules)

Team Members: (Dept. of Physics, Indian Institute of Technology Kanpur, India)

Prof. Satyendra Kumar

Dr. Sanjay K. Ram

Dr. Vivek Shukla

Mr. Girish Gupta

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Organic semiconductors have shown immense potential in terms of their numerous technological applications which were earlier dominated by inorganic semiconductors. These applications started off with electroluminescent devices, but have since diversified to include electronic devices such as transistors as well. The electronic conductivity of these materials lies between that of metals and insulators, spanning a broad range of 10^-9to 10³ (Ωcm)^-1.

Known organic semiconductors can be broadly classified into two groups on the basis of their molecular weight:

• Conjugated polycyclic compounds of molecular weight less than 1000, and
• Heterocyclic polymers with molecular weight greater than 1000.

Polymers are easily deposited as thin films on large areas making them valuable semiconducting materials. Nevertheless, they suffer from a major drawback in that they are not highly soluble in organic solvents, and they lose their mobility upon functionalization to enhance solubility. This has been a major driving force behind the research on small molecules as semiconductors. With small molecules semiconductors, it is possible to control charge transport in a simpler way by modification of various molecular parameters. For example, the ability of these molecules to pack into well-organized polycrystalline films leads to higher mobility compared to polymeric semiconductors.

The study of organic materials (small molecules) in our research group is focused on:

1. Material synthesis and purification

2. Thin film deposition of organic materials (synthesized & commercially available materials) by thermal evaporation technique on the glass/Si/quartz substrates.

3. Structural characterization: AFM, XRD, Spectroscopic Ellipsometry, FTIR

4. Optical Characterization: normal and transient photoluminescence (PL), photoluminescence excitation (PLE), transmissitance and refelectance.

5. Electrical characterization : Temperature dependent dark and photoconductivity on planar and sandwich configuration

6. Device fabrication:

• Organic light emitting diodes (OLED)
• Organic thin film transistors (OTFT)
• Organic solar cells devices

7. Electroluminescence (EL) studies of OLED devices and transistor characteristic studies of OTFT

Organic Light Emitting Diode (OLED)

The device structure of OLED consists of several layers of organic materials sequentially deposited on glass substrate, each layer having a specific purpose that serves to enhance device quality and performance. The schematic representation of an ideal/standard OLED device is shown below.

We have explored several organic materials (small molecules) in our electroluminescent (EL) devices as emitting as well as electron transporting layer like Alq3, Znq2, Cr-doped Alq3, Inq3. The organic materials are usually susceptible to environmental aging and photo-oxidation, which influence their viability for commercial utility. Our studies demonstrate the effects of oxygen, light and environment on these organic materials to enhance the efficiency and lifetime of OLEDs. A simple device structure for these studies, along with the molecular structures of the materials used are shown below.

Organic Thin Film Transistor (OTFT)

Organic thin film transistors (OTFT) have made impressive progress over the past decade. Organic TFTs provide two principal advantages over TFTs based on inorganic semiconductors; they can be fabricated at lower temperatures, and potentially, at significantly lower cost. Low process temperatures, in particular, may allow organic TFTs to be integrated on inexpensive plastic substrates rather than glass. With field effect mobility and current on/off ratio values comparable to amorphous silicon, it becomes increasing likely that organic electronic devices will find use in broad area electronics applications. OTFTs are of interest for such a number of applications as pixel-access devices in active matrix displays, liquid crystal light valves of organic light emitting diodes, switching devices for logic gate memory arrays in smart cards, and low cost integrated circuits on flexible large area substrates.

We have fabricated OTFTs using Pentacene (C₂₂H₁₄), as the active material. Pentacene (C₂₂H₁₄) is a planar molecule composed of five benzene rings. Pentacene has a strong tendency to form molecular crystals. It forms well-ordered films that can be poly or single crystalline depending upon deposition and substrate conditions using vacuum evaporation even at low substrate temperatures. With Pentacene, ordered films are obtained when deposited by thermal evaporation at substrate temperatures as low as 0 ^οC. While the bulk electrical conductivity of acenes such as Pentacene is very low (~ 10^-15 S/cm), Pentacene has been found to have the highest mobilities for hole transport (p-channel). These devices have field-effect mobility as large as 2.2 m²/V-s, comparable to hydrogenated amorphous silicon TFTs. The upper limits in microscopic mobilities of organic molecular crystals, determined at 300 K by time-of-flight experiments, are falling between 1 and 10 cm²/V-s. The high mobility of pentacene is a result of significant orbital overlap from edge-to-face interactions among the molecules in their crystal lattice. The performance of OTFT depends on orientation of molecules, crystal structure, morphology, grain size and defects. In our study we tried to tune these parameters by changing the deposition parameters like nature of substrate (or surface treatment), substrate temperature, deposition rate, film thickness etc during deposition.

OTFT Fabrication

Once the gate oxide is made over Si there are just two possible structures for the source-drain contacts. One is called bottom gate-bottom contact (BG-BC) or bottom electrode TFT design, where drain and source contact metal is patterned on the gate dielectric prior to the active layer deposition. The other is named as bottom gate-top contact (BG-TC) or top electrode TFT design, where both source and drain pads are deposited on the top of an active layer through a shadow mask. The schematic cross sectional view of these structures is as shown below.

Structural and Optoelectronic Properties of Nanostructured Porous Silicon

Team Members: (Dept. of Physics, Indian Institute of Technology Kanpur, India)

Prof. Satyendra Kumar

Dr. Md. Nazrul Islam (Present address: QAED-SRG, Space Applications Centre (ISRO), Ahmedabad, India)

Dr. Sanjay K. Ram

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Under special condition partial electrochemical etching (anodization) of the surface of a crystalline silicon wafer leads to the formation of nanoporous holes in its microstructure, resulting in a large surface to volume ratio in the order of 500m²/cm³. The degree of porosification can be controlled by optimizing the anodization parameters. The material thus achieved, Porous silicon (PS), is a network of nanometer sized Si particles surrounded by voids and space, and is remarkable not only in its ease of fabrication, but also in regards to its properties like complementary metal–oxide–semiconductor (CMOS) compatibility and visible photoluminescence at room temperature.

PS is already being used for a large number of applications which include light-emitting devices like photodetectors and solar cells, and sensing devices. It has also shown great promise either in the form of active layer or in combination with other materials (multilayer). PS is being researched for a whole range of applications like microelectromechanical systems (MEMs), anti-reflective coatings, Bragg reflectors, optical waveguides, chemical and biological sensors.

THEME

The microstructure of porous silicon layers plays a crucial role in determining its opto-electronic properties and possible applications. We have fabricated PS layers with a variety of microstructures having thicknesses ranging from about 1 to 200 microns. Our research has been focused on the microstructural characterization of these PS layers to understand the influence of crystallite size effects, surface effects and surrounding media on the Raman and photoluminescence (PL) spectra. The effect of structural inhomogeneities on the electrical properties and light induced metastabilities were also studied.

In particular, our Raman spectroscopy studies of these PS layers have led to the observation of symmetry forbidden Raman modes at room temperature, depending on the thickness and microstructure. We developed a modified approach to the deconvolution of the Raman scattering data by incorporating the effects of crystallite size distribution (CSD) in the data analysis. In order to understand the PL spectra from silicon nanostructures, a phenomenological model was developed to include both size as well as surface effects. We studied the electron transport properties of these well-characterized porous silicon layers in planar geometry as well as across the c-Si/PS/metal junctions over a wide temperature range from 15 to 450 K.

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Fabrication of Porous Silicon Layers

The PS layers were fabricated by electrochemical anodization of p-Si (100) wafers of 6-10 W.cm resistivity in a Teflon cell using HF (48%) and C₂H₅OH (99.9%) (1:1 by volume) as electrolyte and a platinum disc as a counter electrode. The schematic view of the experimental setup is shown below.

For a uniform current distribution over the exposed area, an Ohmic back contact was provided by thermal evaporation of Al, followed by annealing at 450° C for 1 hour, both procedures carried out in high vacuum conditions. The wafers were anodized at a constant current density of about 10 mA.cm^-2 for times varying from 90 to 120 min under white light illumination, resulting in 30–50 micron thick PS layers. Samples were rinsed in deionized water followed by methanol and subsequently soaked in propanol for few minutes to minimize the structural damage during drying.

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Structural Properties of Porous Silicon

The proper understanding of the PS layer microstructure is vital to the study of the optoelectronic properties of this material. Processing history of PS samples would suggest natural incorporation of disorder and inhomogeneities in the PS network. To understand the microstructure requires measurement of the porosity, thickness, crystallite orientations, sizes and their distribution in PS layers at different length scales. In addition, knowledge of strains in PS layers and PS/c-Si interfaces helps to explain the observed optoelectronic properties.

Scanning Electron Microscopy (SEM)

We used SEM to study the morphology and cross-sections of the PS layers. Our studies show the evolution of the PS layers with anodization time and the effect of changes in different anodization parameters. SEM images of PS layers are shown below which depict our observation of crack initiation in PS layers for shorter anodization times and well-developed cracks and fractured surfaces leading to island formation surrounded by channels for longer anodization times.

X-ray Diffraction (XRD)

The powder XRD studies on the PS layers demonstrated that the remnant porous Si skeleton is single crystalline in nature and has the same orientation as that of the substrate Si. Small lattice misorientation in the crystal planes in XRD spectra increases with increasing thickness of PS layers. Further extensive analyses of XRD data helped us to determine the amount and nature of stress and strain in the PS layers, the mean crystallite sizes and the influence of the anodization parameters on them.

Stress Analysis of Porous Silicon / crystalline Silicon interface

Porous silicon (PS) lattice is expanded from its substrate silicon lattice. This lattice expansion of PS generates lattice mismatch induced compressive strains on PS layers at the PS/substrate interface. The strain relaxes gradually away from the interface resulting the strain gradient from PS/substrate interface to PS surface. The value of average strain depends on the PS layer thickness and becomes the maximum at a certain thickness of PS layer. The change in strain with PS layer thickness is due to the cracking and stress relaxation.

Micro Raman Scattering (RS) Spectroscopy

The major outcomes of our RS studies carried out on PS layers were

- Microstructural characterization of PS layers based on crystallite size distributions with incorporation of CSD in the Raman data analysis methodology.

- Observation of symmetry forbidden Raman modes

The RS data of PS layers reveal spatial inhomogeneities over the anodized surface as well as along the thickness of the samples. These features were explained by correlating the surface morphology from SEM and stress information using XRD. RS spectra show clear evidence of nanocrystalline Si but no distinctive features corresponding to amorphous silicon tissues for all the samples under study.

• Crystallite Size Distribution (CSD) in Si Nanostructures

Crystallite sizes determined using standard phonon confinement model do not correspond to the sizes obtained by XRD analysis. Further, this model fails to describe the PL spectrum measured on the same spot using quantum confinement models. In order to resolve this problem, a Gaussian distribution in crystallite sizes was explicitly included to calculate the Raman spectra of porous silicon in a model developed by Islam and Kumar (J. Appl. Phys. 98 (2005) 024309). The size distribution (mean size and standard deviation) obtained from fitting the Raman data using our procedure was able to predict the PL accurately in the quantum confinement models. Further, the modified Raman intensity analysis was extended to published reports on directly measured crystallite size distribution and RS data on a variety of Si nanostructures (other than anodized PS also). Our Raman analysis is found to produce good agreement with the mean crystallite sizes obtained from X-ray and high-resolution transmission electron microscopy, especially in the size range of mean crystallite sizes between 2 nm and 5 nm.
The phenomenological model not only is useful to obtain the analytic expression for Raman spectral profile from semiconductor nanostructures having a Gaussian distribution in the crystallite sizes, but also helps us envision in a new light the Raman analysis of such materials where a CSD may be present. The presence of large size dispersion in an ensemble of nanocrystallites was found to give rise to amorphous-like low-frequency tails in the Raman line shapes. Assigning such low-frequency tail in Raman line shapes to a-Si during deconvolution of experimental Raman spectra may lead to a misinterpretation.

• Symmetry Forbidden Raman (SFR) Modes in PS

Enhanced microstructural features in thick PS layers led us to the observation of symmetry forbidden Raman scattering modes at room temperature. Information obtained by XRD and SEM on the structural orientation of the PS layer was used to understand the symmetry violations in Raman selection rules. A combination of various mechanisms such as crystallite size effects, lattice mismatch induced micro-misorientations of crystal planes, and multiple reflections and within the porous silicon nanostructures explains our results

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Photo Luminescence (PL) Spectroscopy

In literature various models have been proposed to understand the origin of room temperature PL from nc-Si structures. None of these PL models can explain all the observed experimental results on PL from PS. But a broad consensus has been reached to quantum confinement effect (QCE), which explains most of experimental PL results at least qualitatively. It is generally accepted that the QCE in the nanocrystallites opens up the band gap as well as relaxes the selection rules for radiative transitions, giving rise to above band gap PL in the visible region for crystallite sizes below ~5 nm. However, QCE alone cannot explain the role of various surface treatments and surrounding media.

In our experiments, the PL peak energy was found to vary about ±0.05eV from the mean value with sampling locations on the same samples. However, if we consider the spatial variation of PL peak energy as an error bar, the PL peak energy averaged over the whole PS layer surface remained almost constant for all samples produced over our entire range of anodization times under same anodization conditions. A free fit to our experimental data using simple QC model yields the unreasonable size parameters.

We developed a phenomenological model to analyze the room temperature PL that includes the surface effects and exciton binding energies along with the crystallite size dependent quantum confinement effects. The optical band gap widening is due to QC effects in nanoparticles. On excitation with high-energy photons, photo carriers are generated inside the crystallites and then some relax non-radiatively to the surface states. Subsequently, the relaxed carriers recombine to the ground states radiatively giving PL. We obtained analytical expressions to model the PL line shapes using normal as well as lognormal crystallite size distributions.

Our microstructural studies have revealed that PS layer contains mixed sized crystallites having two different crystallite size distributions. One CSD for smaller crystallites (L<5>L>10 nm). The former CSD only contributes to PL from PS while the latter has no role to play in luminescent properties of PS layers. The quantum confinement and surface states are equally important for efficient visible PL from PS layers. The QCE in nanocrystallites opens up the band gap in nano-particles increases the oscillator strength of radiative transitions while localized surface states take part in radiative de-excitation of photo-excited carriers. The CSD determined from Raman analysis successfully describes the PL line shapes from PS layers using the hybrid (or unified) PL model consisting of QCE and surface states.

This combined mechanism of PL explained most of the observed PL results from PS layers. Further, experimental data on a variety of nanocrystalline silicon (nc-Si) structures with directly measured crystallite size distribution were analyzed satisfactorily. This showed the importance of localized surface states in predicting the PL data from nc-Si. The model is also found useful in understanding the role of surface passivation and surrounding media on the photoluminescence in porous and nanocrystalline Si.

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Electrical Transport in Porous Silicon

For electrical measurements in coplanar configuration, two rectangular Al pads of 1 mm´5 mm sized with a gap of 0.5 mm while for sandwich configuration circular Al pad of 2 mm diameter were thermally evaporated on top of the freshly prepared porous layers in glancing geometry at an angle of 30° between molecular beam and the sample. This precaution prevents shorting of contact between evaporated metal and the silicon skeleton (especially for thick PS layers). In order to make an intimate contact between PS and Al, samples were annealed at ≈200° C for 45 min. All electrical measurements were carried out in a closed-cycle helium cryostat under dark conditions. Care was taken to avoid any light or thermal induced degradation.

Electrical Transport in Coplanar Configuration

We studied the electrical conductivity of electrochemically etched porous silicon over a wide temperature range from 15K to 450K. Applicability of various transport mechanisms has been critically analyzed. Different current transport mechanisms through thick PS layers were found to be predominant in different temperature zones. While the conductivity data above room temperature shows extended state conduction, lowering the temperature leads to Berthelot type conduction (180 - 280 K). Further, Mott’s (140 - 180 K) and Efros-Shklovskii hopping conduction (below 120 K) are found to be operating in lower temperature ranges. A clear cross-over from Mott to Efros-Shklovskii variable range hopping transport is observed at low temperatures.

Electrical Transport in Sandwich Configuration

In our device structure of Al/c‑Si/PS/Al, measured I‑V characteristics may be governed by either c‑Si/PS heterojunction or PS/Al interface, or both. In our studies, we found Al/PS junctions are non-rectifying and quasi-linear whereas Al/PS/c-Si junctions are weakly rectifying. The rectifying behavior is due to PS/c-Si heterojunction. The diode ideality factor (n) is about 8 for bias ≤0.5 V (about 50 for bias ≤5 V) at forward bias and nearly 1 for ≤0.5 V at reverse bias. As the temperature decreases, n at both forward and reverse biases increases. Different current transport mechanisms are found to be operating across the PS/c-Si junctions under forward and reverse biases.

The barrier height measured from I-V data for ≤0.5 V is higher for forward bias than that for reverse bias. I-V results on PS/c-Si junctions are explained by a multi tunneling-recombination model for forward bias. The current transport mechanism in the reverse bias condition is mainly dominated by the carrier generation recombination in the depletion region formed on the PS side. At higher reverse biases, the reverse current transport is governed by the barrier lowering effects. It is found to behave like a Schottky junction with Fermi level pinned to the defect energy levels at the c-Si/PS interface. The conduction band offset is found to be ≈ 0.1 eV. Based on the detailed analysis of I–V data the energy band diagram of the c-Si/PS heterojunction has been presented. Our study provides an easy and useful alternative method of determination of band edge discontinuities in multilayer structures using PS layers.

Persistent Photo Current (PPC) in Porous Silicon

On exposing the samples to infrared filtered white light, PS layers gave an enhanced dark conductivity, known as persistent photo current (PPC), which persisted over long time at 300 K after light illumination was stopped. We studied PPC in details as a function of illumination time, intensity, illumination temperature and sample temperature. We also discovered that PS layers exhibited a decrease in its dark conductivity, similar to Stabler-Wronski effect in a-Si:H, after a prolong illumination. We explained these effects in PS layers by considering inhomogeneities in PS nanostructures.

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Dielectric-Emissive Coatings in High Definition Plasma Display Panels

Team Members: (Dept. of Physics and Samtel Centre for Display Technologies, Indian Institute of Technology Kanpur, India)

Prof. Satyendra Kumar

Dr. Sanjay K. Ram (Sr. Project Scientist)

Dr. Vandana Singh (Sr. Project Scientist)

Mr. Durgesh K. Rai (M. Tech. Student)

Mr. Surajit Sarkar (Ph.D. Student)

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Plasma Display Panels

Alternating current plasma display panel (ac-PDP) technology has ushered in a new era in the manufacture of large, flat, and lightweight displays. The reduced thickness and weight, rich color, with a conveniently wide viewing angle has led the plasma display panels (PDPs) to become an important flat panel display system in the consumer television market.

A PDP works by sandwiching a neon and xenon gas mixture between two sealed glass plates with parallel electrodes deposited on their surfaces. The plates are sealed so that the electrodes form right angles, creating pixels. When a voltage pulse passes between two electrodes, the gas breaks down and produces weakly ionized plasma, which emits UV radiation. The UV radiation activates color phosphors and visible light is emitted from each pixel. A gas discharge in a PDP is a key process for conversion of an electrical representation of an image to visible light information via generation of vacuum ultraviolet (VUV). The schematic diagram of a single pixel of PDP is shown below.

Secondary Electron Emission Coefficient

In ac-PDPs, the metal electrodes are covered with a glass-like dielectric layer upon which a thin sputter-resistant dielectric film is deposited. This protective layer plays a key role in preventing ac-PDPs from sputtering of ions and other plasma particles, like electrons, photons, meta-stable atoms, and emits a large amount of secondary electrons. The secondary electron emission (SEE) coefficient, denoted by γ, provides information on the efficiency of electron emission from the cathode due to ion bombardment. Emission by ions can be one of the major causes of electron emission, but it is never the only cause and often it is not dominant. That is why the coefficient is more often named as effective secondary electron emission coefficient γ_eff.

This SEE yield of the cathode is an important parameter in determining the discharge characteristics in a PDP. A high γ is beneficial in maintaining high plasma density in the PDP cells and is important for lowering of the firing voltage, increase of lifetime, and enhancement of the luminous efficiency. The discharge (firing and sustaining) voltages of PDP are largely dependent on the γ value of the protective layer. These voltages are also important in reducing the product cost.

High Definition Plasma Display Panels (HDPDP) are the future for next generation plasma TVs, which require substantial innovation and improvements in the existing technology platforms to enhance secondary electron emission of protective layers.

Measurement of SEE yield (γ)

Our group’s research is directed towards the measurement of the SEE yield (γ), which is a crucial parameter for characterization of dielectric layers and their applicability in the PDPs. This project is a part of a larger academia-industry collaborative project aiming to develop indigenous HDPDP technology in India.

There is no commercially available set-up to measure the SEE coefficient. We have designed a system, which has been named SEE-tool to measure the effective γ values. In this technique a discharge is produced in a cell (or pixel) (having conditions similar to those existing in real PDPs) in pure noble gases (or their mixtures), and then Paschen curve is obtained that can be matched with model calculations to yield the ion-induced SEE coefficients. The system includes a ultra high vacuum chamber (~10^-9 Torr) inside which the test sample (dielectric-emissive layer coated) is placed during measurements.

The firing voltage in such a setup is uniquely related to the ion-induced γ value, without any fudge factors involved. The breakdown voltage for a particular gas discharge setup depends only on the product pxd, where p is the pressure in the system and d the distance between the electrodes (Paschen law). The γ-coefficient determination is, therefore, based on breakdown voltage measurements as a function of pxd, i.e., the measurement of Paschen curves. Plasma firing voltages vs. the product of pxd are measured using the set up depicted in the figure below.

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Materials for Dielectric-Emissive Coating in HDPDPs

Materials that satisfy the demand for HDPDP must have:

• High secondary electron emission coefficient (γ) of ~ 0.5;
• Near zero sputtering yield for the lifetime (~60,000 hrs);
• High transmission in the visible range with no deterioration over the operating life;
• Acceptable degassing behavior.

In addition, the process for making these films must have high deposition rates and large area scaling capabilities suitable for industrial exploitation of the technology. At present we are exploring the following thin films for suitability in emissive layer in PDPs:

• MgO based thin films by appropriate changes in composition and doping, such as Si, Ca, Sr etc.
• Carbon based thin films such as diamond like carbon and carbon nanotubes.
• Combination of CNTs and MgO thin films.

MgO Thin Films

MgO is a material that is highly suitable for use in plasma-related devices due to its properties like high SEE coefficient (that lowers the operating voltage), high insulation, great tolerance for ion bombardment (increasing the lifetime of panel), high transparency for visible light, and relatively intense exoelectron emission realizing ultra-high dark-room contrast.

We are depositing MgO thin films by DC and pulsed-DC reactive magnetron sputtering technique (picture of unit shown below) using metallic magnesium target and combination of Ar and O₂ gases.

We have achieved MgO thin films with preferred growth along the desired crystalline orientation and controlled growth rates. The films show high optical transmittance in visible range. These films are investigated using different microstructural characterization tools like spectroscopic ellipsometry (SE), atomic force microscopy (AFM), scanning electron microscopy (SEM), and (EDAX). The measured γ of these films are seen to differ in MgO films having different preferential orientations. We have measured the γ on MgO single crystals having a particular type of orientation to know the correlation between γ and crystal orientation. A knowledge about the growth of the preferentially oriented MgO thin films is helpful to optimize the deposition conditions that can lead to the desired types of films. Other aspects of the MgO protective layer that are being explored involve a structural modification in the film, so that the altered physical properties result in improved electrical properties.

Diamond-like carbon

New PDP cell structures have been developed that do not need a transparent protective coating. This will enable the development of a complete new class of non-transparent protective layer materials, like diamond. It will also allow the processing of the dielectric layer in PDP at 500°C, thereby enabling the use of soda-lime glass, even for high definition panels.

DLC is an attractive surface protective layer for dielectric materials inside PDPs due to its high γ and good optical transmission (with proper film optimization). We are preparing DLC films by PECVD technique (with DC and pulsed-DC power supplies) using gas mixture of acetylene (C₂H₂) and hydrogen (H₂). We are investigating the effect of several deposition parameters on DLC film microstructure, its optical properties and SEE. These films are characterized by Raman spectroscopy, SE, FTIR, AFM, SEM, and EDAX.

Carbon Nanotubes

Carbon nanotubes (CNTs) are formed from a single sheet of graphite (a hexagonal lattice of carbon) called “graphene” rolled into a seamless cylinder. Multi-layer techniques used in dielectric-emissive layers in PDPs include MgO layers deposited on CNT. Such bilayer MgO-CNT films show very high γ values, and the strong CNT layer acts as a protective shield for the MgO layer.

We have prepared multi walled carbon nanotubes by PECVD (with both DC and Pulsed DC power supplies) technique using C₂H₂ + H₂ gas mixture. The PECVD technique does not require high synthesis-temperature as it uses heat as well high energy electronsin the plasma to dissociate the feed gas and hence it allows CNT growth at significantly lower temperatures. In addition, the electric field in PECVD method enables the growth of more vertically aligned CNTs than possible with other deposition techniques. Thus microstructural modifications in such layers will be investigated for optimization of γ and other properties.